Diseño De Un Controlador De Memorias DRAM En VHDL

Abstract

DRAM refresh is one of the topic misunderstood by electronic designers due to the many ways refresh can be accomplished. There are two means of performing refresh, distributed and burst; and both can be accomplished by various ways: ROR (Ras Only Refresh). CBR (CAS before Ras) and hidden refresh. Besides, it must be taken into count that it order to reduce the dimension of DRAM packages, the address bus in the DRAMs have been multiplexed; thus, it is also required that the DRAM controller performs address decoding. This paper contains general DRAM controller theory, state machine definitions, timing diagrams and the PLD equations implemented in VHDL used to test the prototyped designed.