Implementation of a Basic ALU 16-bit in CPLD

Authors

  • Guillermo Tejada Muñoz Universidad Nacional Mayor de San Marcos, Facultad de Ingeniería Electrónica y Eléctrica. Lima, Perú

Keywords:

Arithmetic and Logic Unit 16-bit, ALU, CPLD, VHDL, QUARTUS, EPM7128S, UP2 Education Board

Abstract

This paper describes the implementation in a Complex Programmable Logic Device - CPLD of an ALU (Arithmetic and Logic Unit) of 16 bits, which can perform the basic arithmetic operations of addition, subtraction and logical operations AND and XOR. ALU logical blocks have been coded in VHDL (VHSIC-HDL: Very High Speed Integrated Circuit - Hardware Description Language). The free distribution software Quartus II v. 9.1 was used to simulate and program the CPLD EPM7128S, which is embedded in the development system UP2 Education Board.

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Published

2014-06-16

Issue

Vol. 17 No. 1 (2014)

Section

Original papers

License

Copyright (c) 2014 Guillermo Tejada Muñoz

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.

Creative Commons License
Electrónica - UNMSM by Facultad de Ingeniería Electrónica y Eléctrica de la Universidad Nacional Mayor de San Marcos is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
Based on a work at http://revistasinvestigacion.unmsm.edu.pe/index.php/electron/index.

How to Cite

Implementation of a Basic ALU 16-bit in CPLD. (2014). Electrónica - UNMSM, 17(1), 3-10. https://revistasinvestigacion.unmsm.edu.pe/index.php/electron/article/view/15259