Realization on FPGA of Synchronous Sequential Circuits from its State Diagram

Authors

  • Guillermo Tejada Muñoz Facultad de Ingeniería Electrónica y Eléctrica, Universidad Nacional Mayor de San Marcos.Lima, Perú.
  • Steven Jesús Zarzosa Chávez Facultad de Ingeniería Electrónica y Eléctrica, Universidad Nacional Mayor de San Marcos.Lima, Perú.
  • Víctor Benítez Facultad de Ingeniería Electrónica y Eléctrica, Universidad Nacional Mayor de San Marcos.Lima, Perú.

Keywords:

synchronous sequential logic circuits, state diagram, FPGA, XUP Virtex-II Pro, ISE WebPack 10.1, impact, ISE simulador, ModelSim XE, VHDL

Abstract

The following paper is directed at students electronic engineering and related branches in order that they can build synchronous sequential logic circuits within an FPGA, for it only need to describe graphically the functioning of the circuit through its state diagram without the need to know programming in VHDL. As tools are used: the ISE WebPack 10.1 and the development system XUP Virtex-II Pro based on the XC2VP30 chip, which has inserted a FPGA.

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Published

2011-06-13

Issue

No. 27 (2011)

Section

Original papers

License

Copyright (c) 2011 Guillermo Tejada Muñoz, Steven Jesús Zarzosa Chávez, Víctor Benítez

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.

Creative Commons License
Electrónica - UNMSM by Facultad de Ingeniería Electrónica y Eléctrica de la Universidad Nacional Mayor de San Marcos is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 4.0 International License.
Based on a work at http://revistasinvestigacion.unmsm.edu.pe/index.php/electron/index.

How to Cite

Realization on FPGA of Synchronous Sequential Circuits from its State Diagram. (2011). Electrónica - UNMSM, 27, 22-28. https://revistasinvestigacion.unmsm.edu.pe/index.php/electron/article/view/3048