SIMULATION OF MEMORY CACHE

Authors

  • Edgar Ruiz L. Universidad Nacional Mayor de San Marcos. Lima, Peru
  • Eduardo Raffo L. Universidad Nacional Mayor de San Marcos. Lima, Peru

DOI:

https://doi.org/10.15381/idata.v6i2.6031

Keywords:

Cache memory, RAM memory, Uniform distribution, Average access time.

Abstract

This article presents a program simulating the Cache Memory, by considering the system's success percentage and average access time.The program finds the Cache Memory's optimal size with regard to the RAM Memory size, which can be used as a valid criterion in designing both kinds of Memory within a computer.

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Author Biographies

  • Edgar Ruiz L., Universidad Nacional Mayor de San Marcos. Lima, Peru

    Instituto de InvestigaciónFacultad de Ingeniería Industrial.

  • Eduardo Raffo L., Universidad Nacional Mayor de San Marcos. Lima, Peru

    Instituto de InvestigaciónFacultad de Ingeniería Industrial.

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Published

2003-12-31

Issue

Section

Sistemas e Informática

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